1. Field
Exemplary embodiments of the present invention relate to a memory device, and, more particularly, to a technology related to a setting of a memory device.
2. Description of the Related Art
A memory device performs a setting operation for various parameters, modes and the like in an initial operation similarly to other integrated circuit chips. Such a setting operation is performed by a mode register set (MRS) command and an address input corresponding to the mode register set command in most cases.
FIG. 1 is a timing diagram illustrating the operation of a mode register set (MRS) in a per DRAM addressability (PDA) mode in a memory device.
The PDA mode is a mode for supporting each memory device (more exactly, each rank) to perform an independent mode register setting operation. In setting the PDA mode, validity of all mode register set commands is determined according to a signal level of a 0th data pad DQ0. After write latency (WL=AL+CWL, AL: Additive Latency, CWL: Cas Write Latency) from an application time point of the mode register set command, when the signal level of the 0th data pad DQ0 is ‘0’, the applied mode register set command is determined to be valid, and, when the signal level of the 0th data pad DQ0 is ‘1’, the applied mode register set command is determined to be invalid and is ignored.
Referring to FIG. 1, at a time point 101, a mode register set (MRS) command is applied to the memory device. At a time point 102, after a time corresponding to the write latency (WL=AL+CWL) passes from the time point 101, the signal level of the 0th data pad DQ0 is changed to ‘0’ for a predetermined period. Accordingly, the mode register set (MRS) command applied at the time point 101 is determined to be valid, and a setting operation of the memory device using an address (not illustrated) is started for tMRD_PAD (a mode register set command cycle time) from a time point 103.
If the signal level of the 0th data pad DQ0 is continuously maintained to ‘1’ at the time point 102, the mode register set (MRS) command applied at the time point 101 is determined to be invalid and is ignored. In other words, the setting operation of the memory device is not performed.
In the aforementioned PDA mode, it is necessary to determine whether to perform the setting operation using the mode register set command applied at the time point 101 and a signal applied to the 0th data pad at the time point 102. Therefore, in order to support the PDA mode, a plurality of circuits for synchronizing timings of signals applied at different time points should be additionally provided, resulting in an increase in an area of the memory device.